Physical optimizations and corrections techniques such as the post-place optimization, post-route optimization, etc. have been broadly used to achieve timing closure where electronic designs are checked or modified, if necessary, to meet timing requirements. The ever increasing complexity of modern electronic designs (e.g., system on chip or SoC) due to more transistors, more functionality, multiple modes, and multiple corners nevertheless requires longer runtime and larger memory footprint to achieve timing closure. These physical optimization and corrections populate timing data for an electronic design and utilize physics based techniques and a set of views to analyze whether an electronic design meets the timing requirements. A modern electronic design often involves multiple modes and multiple corners, the combination of which thus produces more views for physical optimization to consider and further acerbates the runtime required to achieve timing closure.
Recent development in physical optimizations and corrections attempt to reduce the number of views for timing closure by leveraging global pruning techniques to disable or eliminate views globally so as to reduce the total number of views. Although global pruning does reduce the total number of views somewhat, these conventional approaches are nevertheless not satisfactory because of their conservatism in pruning views across the entire electronic design. For example, a particular view may not be needed for all but one or a few gates in physical optimizations of an electronic design. The global pruning techniques will not remove this particular view simply because this particular view is needed for the only one or a few gates in physical optimizations or corrections.
Therefore, there exists a need for a method, system, and computer program product for multi-mode, multi-corner physical optimization of electronic designs in a more efficient and less computational resource consuming manner.